This invention relates generally to bipolar logic circuits and in particular to emitter coupled logic (ECL) circuits.
ECL circuits are utilized in many large general purpose computers because of the speed at which such circuits operate compared to circuits produced with other technologies such as conductor-insulator-semiconductor field effect transistor (CISFET) technology. ECL gates utilized in current generation ECL integrated circuits (ICs) generally operate with sub-nanosecond signal propagation delays whereas current generation CISFET logic generally operates with about an order of magnitude larger signal propagation delay. While the circuit density (gates per unit of chip area) of ECL ICs is considerably less than CISFET ICs, progress currently being made on new generation ECL technology is expected to increase the circuit density of ECL ICs from a current level of four or five hundred gates per chip to several thousand gates per chip.
One problem faced in increasing ECL circuit density is the power dissipated by each ECL gate and the total power dissipation of an IC comprising an ECL gate array. If the number of ECL gates on an IC chip is substantially increased and each gate draws the same power as in prior generation IC chips, the total power dissipation of the chip will rise dramatically. Such increases in power dissipation probably cannot be tolerated. Generally there are two approaches to attacking the problem of increased power dissipation in high density ECL ICs. One approach involves reducing the DC bias voltages used to operate the chip. The second approach is to increase the values of the resistors utilized in each ECL gate. In some instances a combination of these two approaches may be taken to reduce power dissipation of each gate. Each approach has a potentially adverse impact on ECL technology which must be dealt with.
Reducing bias voltage levels generally requires more careful attention to design considerations such as noise immunity and temperature stability. Increasing the resistance value of resistors utilized in the ECL circuits generally reduces the current available to drive the inherent capacitance seen by the output node of each gate. Where the inherent capacitance of the logic network to be driven by a particular gate is relatively large, such as is typically encountered when the output signal from a particular gate has a large fan-out on the same chip or when the gate is a buffer output gate driving a logic network off-chip through connections to a printed circuit board, increased resistance values can result in substantially increasing the signal propagation delay between the driving gate and the driven network. In the past unacceptably large signal propagation delays have been avoided in ECL technology either by utilizing redundant driving gates or by utilizing additional or lower value pull-down resistors to increase the current available for altering the charge state of the inherent capacitance during a HIGH-TO-LOW signal transition.
Consider for example a typical prior art ECL gate as depicted in FIG. 1 of the accompanying drawings. FIG. 1 depicts a combined NOR and OR logic circuit in which the respective output NOR and OR logic signals are developed at the junctions between emitter-follower transistor 40 and pull-down resistor 45 and the junction between emitter-follower transistor 50 and pull-down resistor 55. As shown, the O.sub.NOR output is adapted to drive a logic network 60 which has an inherent capacitance 61 constituting a load capacitance on the O.sub.NOR output. In the case that both the ECL gate 100 and the logic network 60 are formed on the same IC chip in accordance with current ECL technology, a specific implementation may involve a resistor 45 with a value of about three thousand Ohms and respective bias voltage values V.sub.PD and V.sub.CC of -5.2 volts and zero volts or ground reference. With these resistance and bias voltage values, the ECL circuit of FIG. 1 will operate with sub-nanosecond signal propagation delays only as long as the value of load capacitance 61 does not exceed about two picofarads. For higher value load capacitances associated with logic network 60, two pull-down resistors having a combined value of about 1.5 K Ohms may be utilized. Sub-nanosecond signal propagation delays can be achieved with two such pull-down resistors up to values of load capacitance of about four picofarads. Of course, utilizing two pull-down resistors increases the power dissipation in the logic gate during the steady state levels of the output logic signals.
Consider now the operating characteristics of the prior art circuit of FIG. 1 if the pull-down resistor values are increased to 4 K Ohms and the pull-down voltage V.sub.PD is reduced from -5.2 volts to -3.6 volts to reduce the power consumption of the gate. With these pull-down resistor and pull-down bias voltage values, the prior art circuit of FIG. 1 can achieve sub-nanosecond signal propagation delays only if the value of load capacitance 61 is about one picofarad or less. Accordingly, the use of prior art ECL gates as depicted in FIG. 1 in new generation ECL IC technology may force ECL circuit designers to choose between reducing the signal fan-out from some logic gates by utilizing redundant driving gates or paying the penalty of increased power dissipation by utilizing more than one pull-down resistor or lower value pull-down resistors in the ECL circuits.